In semiconductors that use an oxide as an insulating layer, a high electric field in the oxide can result in a change in the physical properties of the gate oxide of a metal oxide semiconductor (MOS) such that the gate oxide no longer displays its insulating property. This result is generally referred to in the semiconductor industry as “breakdown”. The phrase “hard breakdown” normally refers to a catastrophic, irreversible breakdown of the gate oxide involving thermal effects. The phrase “soft breakdown” normally refers to a breakdown in the MOS structure that results in a leakage current that exceeds a predetermined threshold value. Soft breakdown is also permanent and irreversible, but after soft breakdown, the oxide retains its insulating properties, and conduction through the breakdown spot is not ohmic.
The unreliability of oxides due to breakdown is one of the primary impediments to moving forward along the path predicted by Moore's law. As such, an efficient breakdown testing method is paramount to the success of a semiconductor manufacturer. Because soft breakdown is the prevailing breakdown mode for 90-130 nanometer (nm) technologies, oxide reliability testing now requires small-area test structures and statistically relevant data. Currently, one known testing technique is performed as follows. Small MOS field effect transistors (MOSFETs) are connected to large bond pads. The source and drain of the transistor are tied together to form one terminal, which is connected to ground. A constant voltage is then applied to the gate and the current flowing from between the gate terminal and the ground terminal is measured. If the current exceeds a particular threshold value, soft breakdown is occurring.
One of the disadvantages of this technique is that the transistor area is only about 1 micrometer (μm2) in area while the area required for each of the pads is about 40,000 μm2. Normally, many sites are tested on each wafer. Therefore, a significant amount of area on the wafer is consumed for soft breakdown testing, which results in wasted area that could otherwise be used for transistors. In addition, with this known technique, the transistors are tested serially, which requires the placement of the probes on the pads of each test site to apply the constant voltage and measure the current. Alternatively, equipment may be used to contact many probe pads simultaneously, and to interface the probes to power supplies and measurement electronics. However, such equipment is very expensive.
A need exists for an efficient, easy and cost-effective way to simultaneously test multiple sites for breakdown, wearout or reliability that does not require expensive test equipment.